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 STL100NHS3LL
N-channel 30V - 0.0032 - 22A - PowerFLATTM (6x5) STripFETTM Power MOSFET plus monolithic Schottky
Preliminary Data
Features
Type STL100NHS3LL VDSS 30V RDS(on) < 0.0042 ID 22A(1)
1. This value is rated according to Rthj-pcb
Optimal RDS(on) x Qg trade-off @ 4.5V Reduced switching losses Reduced conduction losses Improved junction-case thermal resistance
PowerFLATTM(6x5)
Application
Switching applications Figure 1. Internal schematic diagram
Description
This product utilizes the latest advanced design rules of ST's proprietary STripFETTM technology and a proprietary process for integrating a monolithic Schottky diode. The new Power MOSFET is optimized for the most important demanding synchronous switch function in DCDC converter for Computer and Telecom.
Table 1.
Device summary
Marking L100NHS3LL Package PowerFLATTM (6 x 5) Packaging Tape & reel
Order code STL100NHS3LL
September 2007
Rev 1
1/9
www.st.com 9
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Electrical ratings
STL100NHS3LL
1
Electrical ratings
Table 2.
Symbol VDS VGS ID
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25C Drain current (continuous) at TC = 100C Drain current (continuous) at TC = 25C Drain current (pulsed) Total dissipation at TC = 25C Total dissipation at TC = 25C Operating junction temperature Storage temperature Value 30 16 22 13.7 100 88 80 4 -55 to 150 Unit V V A A A A W W C
ID (1) ID(2) IDM
(3)
PTOT(1) PTOT(2) Tj Tstg
1. The value is rated accordingly to Rthj-pcb 2. This value is according Rthj-c 3. Pulse width limited by safe operating area
Table 3.
Symbol Rthj-case Rthj-pcb
(1)
Thermal resistance
Parameter Thermal resistance junction-case (drain) Max Thermal resistance junction-pcb Max Value 1.56 31.3 Unit C/W C/W
1. When mounted on FR-4 board of 1inch2, 2 oz. Cu., t<10sec
Table 4.
Symbol IAV EAS
Thermal resistance
Parameter Avalanche current, not repetitive (pulse width limited by Tjmax) Single pulse avalanche energy (starting Tj = 25C, ID=IAV, VDD=24V) Value 10 1.8 Unit A J
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STL100NHS3LL
Electrical characteristics
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 5.
Symbol V(BR)DSS IDSS IGSS VGS(th)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Test conditions ID = 1mA, VGS= 0 VDS = 24V VDS = 16V VDS= VGS, ID = 1mA VGS= 10V, ID= 11A VGS= 4.5V, ID= 11A VGS=10V, ID=11A@125C VGS=4.5V, ID=11A@125C 1 Min. 30 500 100 2.5 0.0032 0.0042 0.004 0.0057 0.005 0.006 Typ. Max. Unit V A nA V
RDS(on)
Static drain-source on resistance
Table 6.
Symbol Ciss Coss Crss Qg Qgs Qgd
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Test conditions Min. Typ. 4200 700 46.2 27 8.5 7.2 35 Max. Unit pF pF pF nC nC nC
VDS=25V, f = 1MHz, VGS=0
VDD = 15V, ID = 22A, VGS = 4.5V (see Figure 3)
3/9
Electrical characteristics
STL100NHS3LL
Table 7.
Symbol
Switching times
Parameter Test conditions VDD = 15V, ID = 11A , RG= 4.7 VGS= 10V, (see Figure 2), (see Figure 7) VDD = 15V, ID = 11A , RG= 4.7 VGS= 10V, (see Figure 2) (see Figure 7) Min. Typ. Max. Unit
td(on) tr
Turn-on delay time Rise time
16 45
ns ns
td(off) tf
Turn-off delay time Fall time
68 8
ns ns
Table 8.
Symbol ISD ISDM VSD (1) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 5A, VGS = 0 ISD = 22V, di/dt = 100A/s VDD = 20V, Tj = 25C (see Figure 4) 30 30 2 Test conditions Min. Typ. Max 22 88 0.75 Unit A A V ns nC A
1. Pulsed: Pulse duration = 300s, duty cycle 1.5%
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STL100NHS3LL
Test circuit
3
Figure 2.
Test circuit
Switching times test circuit for resistive load Figure 3. Gate charge test circuit
Figure 4.
Test circuit for inductive load Figure 5. switching and diode recovery times
Unclamped inductive load test circuit
Figure 6.
Unclamped inductive waveform
Figure 7.
Switching time waveform
5/9
Package mechanical data
STL100NHS3LL
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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STL100NHS3LL
Package mechanical data
PowerFLATTM (6x5) MECHANICAL DATA
mm. DIM. MIN. A A1 A3 b D D1 D2 E E1 E2 E4 e L 0.70 3.43 2.58 4.15 0.35 0.80 TYP 0.83 0.02 0.20 0.40 5.00 4.75 4.20 6.00 5.75 3.48 2.63 1.27 0.80 0.90 0.027 3.53 2.68 0.135 4.25 0.163 0.47 0.013 MAX. 0.93 0.05 MIN. 0.031 TYP. 0.032 0.0007 0.007 0.015 0.196 0.187 0.165 0.236 0.226 0.137 0.103 0.050 0.031 0.035 0.139 0.105 0.167 0.018 MAX. 0.036 0.0019 inch
7/9
Revision history
STL100NHS3LL
5
Revision history
Table 9.
Date 03-Sep-2007
Document revision history
Revision 1 First release Changes
8/9
STL100NHS3LL
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